Synchronous, multi-core processor chips are showing mole regional technology variability at mole advanced technology nodes, and this variability is increasing. To deal with this, people have maintained synchronous operation by changing the system clock frequency and modifying all the local core Vdd settings in older to arrive at a common frequency at which the multi-core chip will run. This common frequency is the lowest-common operating frequency; therefore, much of the possible system performance intrinsic in the faster cores is lost. By some estimates, the degree of the performance loss due to regional variability could be as much as would be lost by backing up the design by an entire technology generation.
It would thus be desirable to overcome the limitations in previous approaches.